📅 About Synopsys 🧑💻
Synopsys is a global leader in the semiconductor IP industry, driving innovation in areas like self-driving cars, AI, and the cloud. We're at the forefront of the "Era of Smart Everything," powering these advancements with cutting-edge chip design and software security technologies.
Synopsys' DesignWare IP portfolio, developed by a team in Lisbon, includes analog and digital IC design engineers, application engineers, and test engineers. Our IP empowers next-generation SoC designers to integrate proven functionality, previously exclusive to large manufacturers. We license this IP to leading semiconductor companies worldwide, offering high-precision, single-function blocks to complete interface subsystems.
🚀 The Role
As an ASIC Analog Modeling Engineer, you'll join a dynamic Digital and Verification Development team. Your key responsibilities will include:
- Contributing to the development and validation of complex digital mixed signals for high-speed interface IP, with a major focus on Analog Schematics.
- Debugging and verifying the Analog schematics, providing support to Analog teams to speed up the verification process.
- Understanding the IP from a system perspective, including Analog and Digital interactions.
- Participating in verification activities of analog designs under the guidance of experienced engineers, exercising judgment to meet specifications.
- Debugging and resolving issues related to analog design malfunctions.
- Gaining experience with mixed signal validation workflows.
- Fostering collaborative relationships with various teams across projects.
- Participating in product/project reviews.
- Preparing and presenting reports outlining technical project outcomes.
🔎 What We're Looking For
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University master’s degree in Electronic/Micro-electronics Engineering.
- Knowledge of IC design flows.
- Analog design knowledge.
- Digital design understanding.
- Understanding of digital verification tools.
- A willingness to learn new things.
- Strong teamwork skills.
- Excellent organizational skills.
- Problem-solving abilities.
- Excellent English communication skills.
👍 Preferred Experience
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2+ years of relevant experience is highly desirable.
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Experience in creating high-quality technical documentation is a plus.
- Experience with analog tools, preferably Synopsys tools.
- A solid understanding of analog design.
- Experience with Verilog/VHDL.
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Proficiency in at least one programming language such as Python, C, C++, or MATLAB.
- Experience with System Verilog/VMM/UVM.
- Familiarity with Unix, Perl, and TCL scripting.
🤝 Our Commitment
Synopsys values inclusion and diversity. We consider all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
💼 Job Details
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Job Category: Engineering
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Job Subcategory: ASIC Digital Design
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Hire Type: Employee
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Country: Portugal
Hopefully, this revised job description format is more engaging and easier to read for potential candidates. Good luck with your hiring process!
Job Category: Engineering